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INTEGRATED CIRCUITS
DATA SHEET
TDA1305T Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
Preliminary specification Supersedes data of September 1994 File under Integrated Circuits, IC01 1995 Dec 08
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
FEATURES * Easy application * 16fs Finite-duration Impulse-Response (FIR) filter incorporated * Selectable system clock (fsys) 256fs or 384fs * I2S-bus serial input format (at fsys = 256fs) or LSB fixed 16, 18 or 20 bits serial input mode (at fsys = 384fs) * Slave-mode clock system * Cascaded 4-stage digital filter incorporating 2-stage FIR filter, linear interpolator and sample-and-hold * Smoothed transitions before and after muting (soft mute) * Digital de-emphasis filter for three sampling rates of 32 kHz, 44.1 kHz and 48 kHz * 12 dB attenuation via the attenuation input control * Double speed mode * 2nd order noise shaper * 96 (fsys = 384fs) or 128 (fsys = 256fs) times oversampling in normal speed mode * 48 (fsys = 384fs) or 64 (fsys = 256fs) times oversampling in double speed mode * Bitstream continuous calibration concept * Small outline SO28 package * Voltage output 1.5 V (RMS) at line drive level * Low total harmonic distortion * No zero crossing distortion * Inherently monotonic * No analog post filtering required * Superior signal-to-noise ratio * Wide dynamic range (18-bit) * Single rail supply (3.4 to 5.5 V). GENERAL DESCRIPTION The TDA1305T is a new generation of filter-DAC which features a unique combination of bitstream and continuous calibration techniques. The converter functions as a ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA1305T SO28 DESCRIPTION plastic small outline package; 28 leads; body width 7.5 mm
TDA1305T
bitstream converter for low signals while large signals are generated using the dynamic continuous calibration technique, thus resulting in low power consumption, small chip size and easy application. The TDA1305T is a dual CMOS DAC with up-sampling filter and noise shaper. The combination of high oversampling up to 16fs, 2nd order noise shaping and continuous calibration conversion ensures that only simple 1st order analog post filtering is required. The TDA1305T supports the I2S-bus data input mode with word lengths of up to 20 bits (at fsys = 256fs) and the LSB fixed serial data input format with word lengths of 16, 18 and 20 bits (at fsys = 384fs). Four cascaded FIR filters increase the oversampling rate to 16 times. A sample-and-hold function increases the oversampling rate to 96 times (fsys = 384fs) or 128 times (fsys = 256fs). A 2nd order noise shaper converts this oversampled data to a bitstream for the 5-bit DACs. The DACs are of the continuous calibration type and incorporate a special date coding. This ensures an extremely high signal-to-noise ratio, superior dynamic range and immunity to process variation and component ageing. Two on-board operational amplifiers convert the digital-to-analog current to an output voltage. Externally connected capacitors perform the required 1st order filtering so that no further post filtering is required. The unique combination of bitstream and continuous calibration techniques, together with a high degree of analog and digital integration, results in a single filter-DAC with 18-bit dynamic range, high linearity and simple low cost application.
VERSION SOT136-1
1995 Dec 08
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
QUICK REFERENCE DATA SYMBOL VDDD VDDA VDDO IDDD IDDA IDDO VFS(rms) (THD + N)/S PARAMETER digital supply voltage analog supply voltage operational amplifier supply voltage digital supply current analog supply current note 1 note 1 note 1 VDDD = 5 V; at code 00000H VDDA = 5 V; at code 00000H CONDITIONS MIN. 3.4 3.4 3.4 - - - 1.425 - - at -60 dB signal level at -60 dB signal level; A-weighted S/N BRns BRds fsys TCFS signal-to-noise ratio at bipolar zero A-weighting; at code 00000H - - - - 100 - - 6.4 - 5.0 5.0 5.0 30 5.5 6.5 1.5 -90 0.003 -44 0.63 -46 0.5 108 - - - 100 x 10-6 TYP.
TDA1305T
MAX. 5.5 5.5 5.5 - 8 9 1.575 -81 0.009 -40 0.1 - - - 3.072 6.144 18.432 -
UNIT V V V mA mA mA V dB % dB % dB % dB Mbits Mbits MHz
operating amplifier supply VDDO = 5 V; current at code 00000H full-scale output voltage (RMS value) total harmonic distortion plus noise-to-signal ratio VDDD = VDDA = VDDO = 5 V at 0 dB signal level
input bit rate at data input fs = 48 kHz; normal speed input bit rate at data input fs = 48 kHz; double speed system clock frequency full scale temperature coefficient at analog outputs (VOL and VOR) operating ambient temperature
Tamb Note
-30
-
+85
C
1. All VDD and VSS pins must be connected to the same supply.
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
BLOCK DIAGRAM
TDA1305T
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
PINNING SYMBOL VDDA VSSA TEST1 PIN 1 2 3 DESCRIPTION analog supply voltage analog ground test input; pin should be connected to ground (internal pull-down resistor) bit clock input word select input data input clock selection 1 input clock selection 2 input digital ground digital supply voltage test input; pin should be connected to ground (internal pull-down resistor) system clock input not connected (this pin should be left open-circuit) not connected (this pin should be left open-circuit) digital ground system clock output de-emphasis on/off; fDEEM 32 kHz, 44 kHz and 48 kHz de-emphasis on/off; fDEEM 32 kHz, 44 kHz and 48 kHz mute input (active LOW) double-speed mode input (active LOW) 12 dB attenuation input (active LOW) left channel output capacitor for left channel 1st order filter function should be connected between pins 22 and 23 capacitor for right channel 1st order filter function should be connected between pins 25 and 24 right channel output internal reference voltage for output channels (0.5VDD) operational amplifier ground operational amplifier supply voltage 5
TDA1305T
BCK WS DATA CLKS1 CLKS2 VSSD VDDD TEST2
4 5 6 7 8 9 10 11
SYSCLKI n.c. n.c. VSSD SYSCLKO DEEM1 DEEM2 MUSB DSMB ATSB VOL FILTCL
12 13 14 15 16 17 18 19 20 21 22 23
FILTCR
24
VOR Vref VSSO VDDO 1995 Dec 08
25 26 27 28
Fig.2 Pin configuration.
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
FUNCTIONAL DESCRIPTION The TDA1305T CMOS digital-to-analog bitstream converter incorporates an up-sampling filter and noise shaper which increase the oversampling rate of 1fs input data to 96fs (fsys = 192fs) or 128fs (fsys = 256fs) in the normal speed mode. In the double speed mode the oversample rate of 1fs input data is increased to 48fs (fsys = 384fs) or 64fs (fsys = 256fs). This oversampling, together with the 5-bit DAC, enables the filtering required for waveform smoothing and out-of-band noise reduction to be achieved by simple 1st order analog post filtering. System clock and data input format The TDA1305T accommodates slave mode only, this means that in all applications the system devices must Table 1 TEST1 0 0 0 0 1 1 1 1 Note 1. Number of clock pulses within half an audio sample. Data input format and system clock. CLKS1 0 0 1 1 0 0 1 1 CLKS2 0 1 0 1 0 1 0 1 DATA INPUT FORMAT I2S up to 20 bits LSB fixed 16 bits LSB fixed 18 bits LSB fixed 20 bits reserved LSB fixed 16 bits LSB fixed 18 bits LSB fixed 20 bits SYSTEM CLOCK 256fs 384fs 384fs 384fs - 384fs 384fs 384fs DATA CLOCK(1) >20 24 24 24 - 32 32 32
TDA1305T
provide a system clock of 256 or 384fs (fs = 32, 44.1 or 48 kHz). The system frequency is selectable by means of pin CLKS1 and pin CLKS2. The SYSCLKO output (pin 16) provides the system clock for external use. The TDA1305T supports the following data input modes: * I2S-bus with data word lengths of up to 20 bits (at fsys = 256fs). * LSB fixed serial format with data word lengths of 16, 18 and 20 bits (at fsys = 384fs). As this format idles on the MSB it is necessary to know how many bits are being transmitted. The input format is shown in Fig.3. Left and right data-channel words are time-multiplexed.
SYSCLKO 256fs 384fs 384fs 384fs - 384fs 384fs 384fs
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2) TDA1305T
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Fig.3 Input formats.
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
Mute Soft mute is controlled by the MUSB at pin 9. When the input is active LOW the value of the samples is decreased smoothly to zero following a cosine curve. To step down the value of the data 32 coefficients are used, each one being used 31 times before stepping onto the next. When MUTE is released (pin 19 = HIGH), the samples are returned to the full level again following a cosine curve with the same coefficients being used in the reverse order. Mute is synchronized to prevent operation in the middle of a word. De-emphasis A digital de-emphasis is implemented for three sample rates (32, 44.1 and 48 kHz). By selecting DEEM1 and DEEM2 de-emphasis can be applied by means of a FIR filter. Time constants of the de-emphasis are 50 s and 15 s. De-emphasis is synchronized to prevent operation in the middle of a word. The de-emphasis deviation from ideal 50 s and 15 s de-emphasis is given in Table 4. Table 2 DEEM1 0 0 1 1 Attenuation Attenuation is controlled by the ATSB input (pin 21). When the input is active LOW the sample is multiplied by a coefficient that provides 12 dB attenuation. If the input is HIGH the multiplication factor is 1. Attenuation is synchronized to prevent operation in the middle of a word. Double-speed mode Double speed is controlled by the DSMB input (pin 20). When the input is active LOW the device operates in the double-speed mode. De-emphasis. DEEM2 0 1 0 1 CONDITION de-emphasis disabled de-emphasis for fs = 32 kHz de-emphasis for fs = 4.1 kHz de-emphasis for fs = 48 kHz
TDA1305T
Oversampling filter (normal-speed mode) In the normal-speed mode the oversampling filter consists of: * A 91st order half-band low-pass FIR filter which increases the oversampling rate from 1 time to 2 times. * A 23rd order quarter band low-pass FIR filter which increases the oversampling rate from 2 times to 8 times. * A linear interpolation section which increases the oversampling rate to 16 times. This removes the spectral components around 8fs. * A sample-and-hold section which provides another 6 times oversampling to 96 times. The zero-order hold characteristic of this sample-and-hold section plus the 1st order analog filtering remove the spectral components around 16fs. Pass-band ripple and stop-band attenuation for normal-speed are given in Table 3. Oversampling filter (double-speed mode) In the double-speed mode the oversampling filter consists of: * A 51st order half-band low-pass FIR filter which increases the oversampling rate from 1 time to 2 times. * A 7th order half-band low-pass FIR filter which increases the oversampling rate from 2 times to 4 times. * A linear interpolation section which increases the oversampling rate to 8 times. This removes the spectral components around 4fs. * A sample-and-hold section which provides another 6 times oversampling to 48 times. The zero-order hold characteristic of this sample-and-hold section plus the 1st order analog filtering remove the spectral components around 8fs. Pass-band ripple and stop-band attenuation for double-speed are given in Table 3.
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
Noise shaper In the normal speed mode the 2nd order digital noise shaper operates at 96fs (fsys = 384fs) or 128fs (fsys = 256fs). The digital noise shaper operates at 48fs (fsys = 384fs) or 64fs (fsys = 256fs) in double-speed mode. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique used in combination with a special data coding enables extremely high signal-to-noise ratios to be achieved. The noise shaper outputs a 5-bit pulse duration modulation (PDM) bitstream signal to the DAC. Continuous calibration DAC The dual 5-bit DAC uses the continuous calibration technique. This method, based on charge storage, involves exact duplication of a single reference current source. In the TDA1305T, 32 such current sources plus 1 spare source are continuously calibrated. The spare source is included to allow continuous converter operation. The DAC receives a 5-bit data bitstream from the noise shaper. This data is then converted so that only small currents are switched to the output during digital silence
TDA1305T
(input 00000H). Using this technique extremely high signal-to-noise performance is achieved. Operational amplifiers High precision, low-noise amplifiers together with the internal conversion resistors RCONV1 and RCONV2 convert the converter output current to a voltage capable of driving a line output. This voltage is available at VOL and VOR (1.5 V RMS typical). Connecting external capacitors CEXT1 and CEXT2 between FILTCL and VOL and between FILTCR and VOR respectively provides the required 1st order post filtering for the left and right channels (see Fig.1). The combinations of RCONV1 with CEXT1 and RCONV2 with CEXT2 determine the 1st order fall-off frequencies. Internal reference circuitry Internal reference circuitry ensures that the output voltage signal is proportional to the supply voltage, thereby maintaining maximum dynamic range for supply voltages from 3.4 to 5.5 V and making the circuit also suitable for battery-powered applications.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VDDA VDDO Txtal Tstg Tamb Ves PARAMETER digital supply voltage analog supply voltage operational amplifier supply voltage maximum crystal temperature storage temperature ambient operating temperature electrostatic handling note 1 note 2 Notes 1. Human body model; C = 100 pF, R = 1500 , V = 2000 V, 3 pulses positive and 3 pulses negative. 2. Machine model; C = 200 pF, R = 10 , L = 0.5 H. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 75 UNIT K/W CONDITIONS - - - - -65 -30 -2000 -200 MIN. MAX. 7.0 7.0 7.0 +150 +150 +85 +2000 +200 V V V C C C V V UNIT
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
QUALITY SPECIFICATION
TDA1305T
In accordance with "SNW-FQ-611E". The number of this quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9398 510 63011. DIGITAL CHARACTERISTICS VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supply VDDD IDDD VDDA IDDA VDDO IDDO RR digital supply voltage digital supply current analog supply voltage analog supply current operational amplifier supply voltage operational amplifier supply current ripple rejection to VDDA system frequency LOW level input voltage HIGH level input voltage input leakage current input capacitance clock cycle time fsys = 384fs fsys = 256fs VIL VIH ILI Ci VOL VOH tr tf CL LOW level input voltage HIGH level input voltage input leakage current input capacitance note 3 note 3 note 4 note 1 VDDD = 5 V; at code 00000H note 1 VDDA = 5 V; at code 00000H note 1 VDDO = 5 V; at code 00000H note 2 3.4 - 3.4 - 3.4 - - 5.0 30 5.0 5.5 5.0 6.5 25 5.5 40 5.5 8 5.5 9 - V mA V mA V mA dB PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
System clock input fsys VIL VIH ILI Ci Tcy fsys = 384fs fsys = 256fs note 3 note 3 note 4 9.6 6.4 -0.5 0.8VDD - - 104 156 -0.5 0.7VDD - - 16.93 11.29 - - - - 59.1 88.6 - - - - - - - - - 18.4 12.28 0.2VDD VDD + 0.5 10 10 54.2 81.3 MHz MHz V V A pF ns ns
Digital inputs; WS, BCK, DATA, DSMB, MUSB, DEEM1, DEEM2, ATSB, CLKS1, CLKS2, TEST1 and TEST2 0.3VDD VDD + 0.5 10 10 V V A pF
Digital output; CDEC LOW level output voltage HIGH level output voltage output rise time output fall time load capacitance IOL = 0.4 mA IOH = -0.2 mA note 5 note 5 0 VDD - 0.5 - - - 0.5 VDD 20 20 30 V V ns ns pF
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
SYMBOL PARAMETER CONDITIONS - - 25 50 - - 55 55 40 10 40 10 MIN. TYP. - - 48 96 20 20 - - - - - -
TDA1305T
MAX.
UNIT
Serial input data timing (see Fig.4) fBCK fWS tr tf tH tL tsu th tsuWS thWS Notes 1. All VDD and VSS pins must be connected externally to the same supply. 2. Vripple = 1% of supply voltage; fripple = 100 Hz. Ripple rejection RR to VDDA is dependent on the value of the external capacitor (CEXT3 in Fig.1) connected to Vref. The value here assumes that CEXT3 = 1 F. 3. Minimum VIL and maximum VIH are peak values to allow for transients. 4. ILImni measured at VI = 0 V; ILImax measured at VI = 5.5 V. 5. Reference levels = 10% and 90%. ANALOG CHARACTERISTICS VDD = VDDA = VDDO = 5 V; VSS = 0 V; Tamb = 25 C; unless otherwise specified. SYMBOL Reference values Vref RCONV reference voltage level current-to-voltage conversion resistor 2.45 1.6 2.5 2.2 2.55 2.8 V k PARAMETER CONDITIONS MIN. TYP. MAX. UNIT bit-clock input (data input rate) frequency word select input frequency rise time fall time bit clock time HIGH bit clock time LOW data set-up time data hold time word select set-up time word select hold time fsys = 384fs fsys = 256fs normal speed double speed 48fs 64fs 44.1 88.2 - - - - - - - - MHz MHz kHz kHz ns ns ns ns ns ns ns ns
Analog outputs RES VFS(rms) resolution full-scale output voltage (pins 23 and 25) (RMS value) output voltage DC offset with respect to reference voltage level Vref full scale temperature coefficient - 1.425 - 1.5 18 1.575 bit V
VOFF
-80
-65
-50
mV
TCFS
-
100 x 10-6
-
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
SYMBOL PARAMETER CONDITIONS - - - - - - - - 100 85 - - 3 - MIN. -90 0.003 -44 0.63 -46 0.5 -90 0.003 108 100 0.2 10 - - TYP.
TDA1305T
MAX. -81 0.009 -40 1.0 - - -81 0.003 - - 0.3 - - 200
UNIT dB % dB % dB % dB % dB dB dB k pF
(THD + N)/S total harmonic distortion plus at 0 dB input level; noise-to-signal ratio note 1 at -60 dB input level; note 2 at -60 dB input level; A-weighted; note 3 at 0 dB input level; (20 Hz to 20 kHz); note 4 S/N cs VO ZO RL CL Notes signal-to-noise ratio at bipolar zero channel separation unbalance between outputs dynamic output impedance output load resistance output load capacitance A weighted; at code (00000H)
1. Measured with a 1 kHz, 0 dB, 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S measured over a bandwidth of 20 Hz to 20 kHz. 2. Measured with a 1 kHz, -60 dB, 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S measured over a bandwidth of 20 Hz to 20 kHz. For 16-bit input signals, the performance is limited to the theoretical maximum. 3. Measured with a 1 kHz, -60 dB, 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S measured over a bandwidth of 20 Hz to 20 kHz and filtered with a A-weighted characteristic. For 16-bit input signals, the performance is limited to the theoretical maximum. 4. Measured with a sine wave from 20 Hz to 20 kHz generated at a sampling rate of 48 kHz. The (THD + N)/S measured over a bandwidth of 20 Hz to 20 kHz. TEST AND APPLICATION INFORMATION Filter characteristics (theoretical values) Table 3 Normal speed filter characteristics. SAMPLE FREQUENCY 44.1 kHz 32 kHz Stop band 44.1 kHz RANGE 0 to 20 kHz 14.5 to 15 kHz 24.1 to 150 kHz 150 kHz to infinity 32 kHz 17 to 17.5 kHz typical worst case typical worst case CONDITIONS CHARACTERISTICS 0 0.025 dB -0.15 dB (min.) -60 dB (max.) -57 dB (max.) -57 dB (max.) -47 dB (max.) -40 dB (max.)
ITEM Pass band
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
De-emphasis filter characteristics (theoretical values) Table 4 De-emphasis deviation from ideal 50 s to 15 s de-emphasis network. SAMPLE FREQUENCY 44.1 and 48 kHz 32 kHz Phase deviation 44.1 and 48 kHz 32 kHz RANGE 0 to 18 kHz 18 to 20 kHz 0 to 13 kHz 13 to 15 kHz 0 to 15 kHz 15 to 20 kHz 0 to 9 kHz 9 to 15 kHz Double-speed characteristics Table 5 Double-speed filter characteristics. RANGE 0 to 17 kHz 17 to 20 kHz Stop band 24.1 to 150 kHz 150 kHz to infinite typical worst case typical worst case CONDITIONS
TDA1305T
ITEM Gain deviation
CHARACTERISTICS 0 0.05 dB 0.12 dB (max.) 0 0.06 dB 0.22 dB (max.) 10 deg (max.) 15 deg (max.) 10 deg (max.) 16 deg (max.)
ITEM Pass band
CHARACTERISTICS 0 0.075 dB -0.3 dB (min.) -47 dB (max.) -45 dB (max.) -33 dB (max.) -25 dB (max.)
Fig.4 Timing of input signals.
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
APPLICATION INFORMATION
TDA1305T
Fig.5 Application diagram.
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
A typical application diagram is illustrated in Fig.5. The left and right channel outputs can drive a line output directly. The series inductor (L) in the digital supply line, though not strictly necessary, helps to reduce crosstalk between the digital and analog circuits. In Fig.6 measurements were taken with an 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S was measured over a bandwidth of 20 Hz to 20 kHz. The graph was constructed from average
TDA1305T
measurement values of a small amount of engineering samples. No guarantee for typical values is implied. In Fig.6 measurements were taken with an 18-bit sine wave generated at a sampling rate of 48 kHz. The (THD + N)/S was measured over a bandwidth of 20 Hz to 20 kHz and filtered with A-weighted characteristics. The graph was constructed from average measurement values of a small amount of engineering samples. No guarantee for typical values is implied.
(1) Level = -60 dB. (2) Level = 0 dB.
Fig.6 Total harmonic distortion as a function of signal frequency.
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
TDA1305T
Fig.7 Total harmonic distortion as a function of signal level; (A-weighted).
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
PACKAGE OUTLINE SO28: plastic small outline package; 28 leads; body width 7.5 mm
TDA1305T
SOT136-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 A1 pin 1 index Lp L 1 e bp 14 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 18.1 17.7 0.71 0.69 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT136-1 REFERENCES IEC 075E06 JEDEC MS-013AE EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
TDA1305T
Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA1305T
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. (31)40-2788399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. (852)2319 7888, Fax. (852)2319 7700 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (45)32 88 26 36, Fax. (45)31 57 19 49 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (358)0-615 800, Fax. (358)0-61580 920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 51 40, 20035 HAMBURG, Tel. (040)23 53 60, Fax. (040)23 53 63 00 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)7640 000, Fax. (01)7640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5130, Fax. (03)3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. (040)2783749, Fax. (040)2788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (63) 2 816 6380, Fax. (63) 2 817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430, Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494 Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (66) 2 745-4090, Fax. (66) 2 398-0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 27 70, Fax. (0212)282 67 07 Ukraine: Philips UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. 380-44-4760297, Fax. 380-44-4766991 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCD47 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/50/02/pp20 Document order number: Date of release: 1995 Dec 08 9397 750 00517

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